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Faculty

Heranmoy Maity



Designation: Assistant Professor

Ph.D (Engineering) Pursuing from National Institute of Technology Durgapur, M.Tech (Electronics and Communication Engineering) from Kalyani Govt. Engineering College Nadia under WBUT, West Bengal, India, in 2010. Total teaching experience is around 13 years out of which 10 years at NSHM Knowledge Campus Durgapur. He is a life member of IE(I), Member of IEEE, IAENG, IERP etc. He has many publications in reputed journal and conference. His research interest in reversible logic circuit design, quantum computing, power line communication, VLSI, cryptograph.

Academic Experience: Total 13 years of teaching and research experience in different organization.


Educational Credentials:

PhD. in Engineering (Pursuing), NIT Durgapur; M.Tech (ECE), WBUT; B.Tech (ECE), WBUT

Research Highlights: He has 10 international journal and 5 international conference publications.

Significant Professional Achievements: Member (M-1606543) of Institution of Engineers (India), Member (# 93645373) of IEEE, Member (249538) of International Association of Engineers (IAENG),

List of Publications:

Journal – • Heranmoy Maity, Sudipta Banerjee, Arindam Biswas, Anita Pal and Anup Kr. Bhattacharjee, “Design of Reversible Shift Register Using Reduced Number of Logic Gate”, Micro and Nanosystems, (2019). (Accepted) (Scopus) DOI: 10.2174/1876402911666190617112734
• Heranmoy Maity, Arindam Biswas, Anup Kr. Bhattacharjee and Anita Pal, “The Quantum Cost Optimized Design of 2:4 Decoder Using New Reversible Gate”, Micro and Nanosystems, (2019). (Accepted) (Scopus) DOI: 10.2174/2213476X06666190916141330
• Heranmoy Maity, Arindam Biswwas, Anup. Kr. Bhattacharjee & Anita Pal, “Design of Reversible Combinational Circuits Using New Reversible Logic Gate”, Journal of Engineering Science and Technology Review, Vol. 11, No. 5 (2018), pp. 170 – 172. (Scopus)
• Heranmoy Maity, Arindam Biswas, Anita Pal and Anup Kr. Bhattacharjee, “Design of BCD to Excess-3 Code Converter Circuit with Optimized Quantum Cost, Garbage Output and Constant Input Using Reversible Gate”, International Journal of Quantum Information, Vol. 16, No. 7 (2018) 1850061 (5 pages). SCI (E)
• Heranmoy Maity, Arindam Biswas, Anup Kr. Bhattacharjee and Anita Pal, “Quantum Cost Optimized Design of 4-bit Reversible Universal Shift Register Using Reduced Number of Logic Gate”, International Journal of Quantum Information, Vol. 16, No. 2 (2018) 1850016 (8 pages). SCI (E)
• Heranmoy Maity, Arijit Kr. Barik, Arindam Biswas, Anup Kr. Bhattacharjee and Anita Pal, “Design of Quantum Cost, Garbage Output and Delay Optimized BCD to Excess-3 and 2’s Complement Code Converter”, Journal of Circuits, System and Computers, Vol. 27, No. 12 (2018) 1850184 (11 pages). SCI (E)
• Heranmoy Maity, Arindam Biswas and Anup Kr. Bhattacharjee, “Low Cost Design of MOD-8 Synchronous UP/DOWN Counter using Reversible Logic Gate”, International Journal for Scientific Research & Development, Vol. 4, Issue 04, 2016, pp. 9 – 11.
• Shashank Kumar Singh, Heranmoy Maity and Abhijit Dey, “A Novel Design of MOD-8 Synchronous UP/DOWN Counter Using Reversible Gate”, International Journal Of Scientific Research And Education, Vol. 2, Issue 9, 2014, pp. 1968 – 1976.
• Heranmoy Maity, Shashank Kumar Singh, Abhijit Dey and Anu Debnath, “Design of 4 Bit Johnson Counter using Reduced Number of Reversible Logic Gates”, International Journal for Scientific Research & Development, Vol. 3, Issue 07, 2015, pp. 778 – 779.
• Heranmoy Maity, Abhijit Dey and Shashank Kumar Singh, “A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gates”, International Journal for Scientific Research & Development, Vol. 2, Issue 08, 2014, pp. 119 – 121. Conference Proceeding: • H. Maity, A. Biswwas, A. K. Bhattacharjee & A. Pal, “The Quantum Cost, Garbage Outputs and Constant Input Optimized Implementation of 2:4 Decoder Using Peres Gate”, IEEE Int. Conf. on Device for Integrated Circuit (DevIC 2019), Kalyani India March 2019. (Accepted). DOI: 10.1109/DEVIC.2019.8783274
• H. Maity, A. Biswwas, A. Pal and A. K. Bhattacharjee, “Quantum Cost Optimized Design of Reversible 2’s Complement Code Converter”, 1st 2018 IEEE Electron Device Kolkata Conference (2018 IEEE EDKCON), Kolkata, India, 24-25 November 2018. (Accepted). DOI: 10.1109/EDKCON.2018.8770220
• H. Maity, A. Biswwas, A. K. Bhattacharjee and Anita Pal, “Design of Quantum Cost Efficient 4-Bit Reversible Universal Shift Register”, IEEE Int. Conf. on Device for Integrated Circuit (DevIC 2017), Kalyani India, 23-24 March 2017, pp: 44-47.
• A. Agarwal, H. Maity, A. Biswwas, S. S. Mandal and A. Rai, “Design of 4-Bit Reversible Johnson Counter with Optimized Quantum Cost, Delay, and Number of Gate”, 1st International Conference on Emerging Trends in Engineering and Science (ETES-2018), Lecture Notes in Networks and Systems (Springer), Asansol, India, 23 -24 March 2018. DOI: 10.1007/978-981-13-3122-0_54
• H. Maity, A. Biswwas and A. K. Bhattacharjee, “Design of quantum cost efficient MOD-8 synchronous UP/DOWN counter using reversible logic gate”, International Conference on Computational Science and Engineering (ICCSE 2016), Kolkata, India, 4-6 November 2016, pp:3 – 6